Memory system that carries out soft bit decoding

ABSTRACT

A memory system includes a nonvolatile semiconductor memory and a controller. The controller is configured to maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and carry out decoding of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2016-178783, filed Sep. 13, 2016, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a memory system.

BACKGROUND

Soft-decision decoding is known as a method of correcting an errorincluded in data read from a semiconductor memory.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a memory system according to a firstembodiment.

FIG. 2 is a block diagram of an ECC circuit in the memory systemaccording to the first embodiment.

FIG. 3 is a graph illustrating threshold distributions of memory cells.

FIG. 4 is a graph illustrating overlapped threshold distributions of thememory cells.

FIG. 5 is a graph illustrating a shift of a threshold distribution ofthe memory cells.

FIG. 6 illustrates a structure of an order set table according to thefirst embodiment.

FIG. 7 is a flowchart illustrating soft-decision processing according tothe first embodiment.

FIG. 8 illustrates a sequence of data reading according to the firstembodiment.

FIG. 9 is a block diagram of an ECC circuit according to a secondembodiment.

FIG. 10 illustrates a structure of an order set table according to thesecond embodiment.

FIG. 11 is a flowchart illustrating soft-decision processing accordingto the second embodiment.

FIG. 12 is a block diagram of an ECC circuit according to a thirdembodiment.

FIG. 13 illustrates a structure of an order set table according to thethird embodiment.

FIG. 14 is a flowchart illustrating soft-decision processing accordingto the third embodiment.

FIG. 15 is a block diagram of the ECC circuit according to the thirdembodiment.

FIG. 16 illustrates a structure of the order set table according to thethird embodiment.

FIG. 17 is a block diagram of an ECC circuit according to a fourthembodiment.

FIG. 18 illustrates a structure of an order set table according to thefourth embodiment.

FIG. 19 is a flowchart illustrating soft-decision processing accordingto the fourth embodiment.

FIG. 20 illustrates a plane layout of memory cell arrays according tothe fourth embodiment.

FIG. 21 is a cross-sectional diagram and an equivalent circuit diagramof a NAND string according to the fourth embodiment.

FIG. 22 is a block diagram of an ECC circuit according to a fifthembodiment.

FIG. 23 illustrates a structure of a history table according to thefifth embodiment.

FIG. 24 is a flowchart illustrating soft-decision processing accordingto the fifth embodiment.

FIG. 25 illustrates a structure of a history table according to a sixthembodiment.

FIG. 26 is a flowchart illustrating soft-decision processing accordingto the sixth embodiment.

FIG. 27 illustrates a structure of a history table according to aseventh embodiment.

FIG. 28 is a flowchart illustrating soft-decision processing accordingto the seventh embodiment.

DETAILED DESCRIPTION

An embodiment provides a memory system that can improve operationreliability.

In general, according to an embodiment, a memory system includes anonvolatile semiconductor memory and a controller. The controller isconfigured to maintain a plurality of log likelihood ratio (LLR) tablesfor predicting a value of data read from the nonvolatile semiconductormemory, count a number of times that each of write operations, eraseoperations, and read operations have been carried out with respect toeach unit storage region of the nonvolatile semiconductor memory,determine an order in which the LLR tables are referred to, based on thecounted number of the read operations and one of the counted number ofthe write operations and the counted number of the erase operations,which correspond to a target unit storage region of a read operation,and carryout decoding of data read from the target unit storage regionof the read operation, using one of the LLR tables selected according tothe determined order.

Embodiments will be described below with reference to the drawings.Moreover, in the following description, elements having the samefunction or configuration are described with the same reference numeral.

1. First Embodiment

A memory system according to a first embodiment is described. As anexample, a memory system that includes a NAND flash memory as asemiconductor memory device will be described.

1.1 Configuration 1.1.1 Overall Configuration of the Memory System

First, an overall configuration of the memory system according to thepresent embodiment is generally described with reference to FIG. 1.

As illustrated, a memory system 1 includes a NAND flash memory 100 and acontroller 200. The NAND flash memory 100 and the controller 200 mayconfigure a single semiconductor device, and examples of such deviceinclude a memory card, such as a SD™ card, a solid state drive (SSD),and the like.

The NAND flash memory 100 includes a plurality of memory cells andstores data in a nonvolatile manner. The controller 200 is connected tothe NAND flash memory 100 via a NAND bus and to a host apparatus 300 viaa host bus. The controller 200 controls the NAND flash memory 100, thatis, in response to a command that is received from the host apparatus300, accesses the NAND flash memory 100. The host apparatus 300 is, forexample, a digital camera, a personal computer, or the like, and thehost bus is, for example, a bus in compliance with an SD™ interface. TheNAND bus performs transmission and reception of a signal conforming to aNAND interface.

1.1.2. Configuration of the Controller 200

A configuration of the controller 200 is described in detail withreference to FIG. 1. As illustrated in FIG. 1, the controller 200includes a host interface circuit 210, a built-in memory (RAM) 220, aprocessor (CPU) 230, a buffer memory 240, a NAND interface circuit 250,and an error checking and correcting circuit (ECC) circuit 260.

The host interface circuit 210 is connected to the host apparatus 300via the host bus and transfers a command and data that are received fromthe host apparatus 300 to the processor 230 and the buffer memory 240,respectively. Furthermore, in response to a command from the processor230, data in the buffer memory 240 are transferred to the host apparatus300.

The processor 230 controls operations of the entire controller 200. Forexample, in response to a writing command from the host apparatus 300,the processor 230 issues a writing command to the NAND interface circuit250. This is true also for reading and erasing. Furthermore, theprocessor 230 performs various processing operations for managing theNAND flash memory 100, such as wear leveling.

The NAND interface circuit 250 is connected to the NAND flash memory 100via the NAND bus, and manages communication with the NAND flash memory100. Then, based on a command that is received from the processor 230,the NAND interface circuit 250 transmits various signals to the NANDflash memory 100 and receives various signals from the NAND flash memory100.

The buffer memory 240 temporarily retains write data and read data.

The built-in memory 220 is a semiconductor memory, for example, such asa DRAM or a SRAM, and is used as a working region for the processor 230.Then, the built-in memory 220 retains firmware for managing the NANDflash memory 100, various management tables, or the like.

The ECC circuit 260 performs error detection and error correctionprocessing relating to data stored in the NAND flash memory 100. Thatis, the ECC circuit 260 generates an error correction code when writingdata, attaches the generated error correction code to the write data,and decodes data when reading the data. As error correction codes, ahard-decision decoded code, such as a BCH code or a Reed-Solomon code(RS), and a soft-decision decoding code, such as a low-densityparity-check (LDPC) code, can be used. The ECC circuit 260 will bedescribed in more detail in 1.1.4.

1.1.3 Configuration of the NAND Flash Memory 100

Next, a configuration of the NAND flash memory 100 is described. Asillustrated in FIG. 1, the NAND flash memory 100 includes a memory cellarray 110, a row decoder 120, a driver circuit 130, a sense amplifier140, an address register 150, a command register 160, and a sequencer170.

The memory cell array 110 includes a plurality of blocks BLK each ofwhich includes a plurality of nonvolatile memory cells that are arrangedin rows and columns. In FIG. 1, as one example, four blocks BLK0 to BLK3are illustrated. The memory cell array 110 stores data received from thecontroller 200.

The row decoder 120 can select any one of the blocks BLK0 to BLK3 andselect a row in the selected block BLK.

The driver circuit 130 supplies a voltage to the selected block BLKthrough the row decoder 120.

When reading data, the sense amplifier 140 senses voltages of data thatare read from the memory cell array 110, and performs a necessaryarithmetic operation. Then, data DAT (read data) are output to thecontroller 200. When writing data, write data DAT received from thecontroller 200 are transferred to the memory cell array 110.

The address register 150 retains an address ADD that is received fromthe controller 200. The command register 160 retains a command CMD thatis received from the controller 200.

Based on the command CMD that is retained in the command register 160,the sequencer 170 controls operations of the entire NAND flash memory100.

1.1.4 ECC Circuit 260

Next, the ECC circuit 260 that is included in the controller 200 isdescribed in detail. FIG. 2 is a block diagram of the ECC circuit 260,in particular elements thereof related to data decoding. As illustrated,the ECC circuit 260 includes a decoder 261, a memory 262, and a selector263, which are connected to one another in such a manner thatcommunication is possible.

The decoder 261 performs hard-decision decoding processing andsoft-decision decoding processing on data read from the NAND flashmemory 100, and transmits the decoded data to the host apparatus 300.During the soft-decision decoding processing, based on a log likelihoodratio (LLR), the decoder 261 performs an iterative calculation based ona probability. Then, based on the calculation, an error is detected andcorrected. The log likelihood ratio (LLR) is information indicatingreliability (probability) of data that are read using a certain readvoltage, and is obtained using a log likelihood ratio table (LLR table).

The LLR table will be briefly described hereinafter. FIG. 3 illustratesthreshold distribution of memory cells, and, for brief description,illustrates a case where one-bit data are retained. As described, memorycells retain data according to a threshold voltage. In FIG. 3, memorycells that retain data “1” has a low threshold voltage and memory cellsthat retain data “0” has a high threshold voltage.

Threshold voltages of memory cells retaining data are distributed withina range up to a given certain width. This is referred to as a thresholddistribution. Ideally, it is desirable that a threshold distribution ofdata “0” and a threshold distribution of data “1” are separated fromeach other. In this case, as described in FIG. 3, the data “0” and thedata “1” can be correctly determined by reading data using a voltageVCGRV between the two threshold distributions as the read voltage.

However, a width of the threshold distribution may broaden due tovarious reasons after data writing, and, as illustrated in FIG. 4, twothreshold distributions may overlap. In a case where the thresholddistributions overlap in this manner, a reading error may occur.According to the soft-decision processing, such as the LDPC, which isdescribed above, the ability to correct an error can be improved byperforming decoding using the LLR table. The LLR table is a table thatindicates a relationship between each range of a threshold voltage andthe LLR when the threshold voltage that the memory cell can take isdivided into the plurality of ranges. In an example shown in FIG. 4, arange between V1 and V2, a range between V2 to V3, or the like isequivalent to a range of the threshold voltages described above. Duringthe soft-decision processing, soft bit reading is performed. The softbit reading in FIG. 4 is a reading operation using voltages V1 to V7 asthe read voltage. With a soft bit obtained through this soft bitreading, a range of the threshold voltages described above that areamong threshold voltages of each memory cell can be known, and the LLRthat corresponds to the range of the threshold voltages can be obtainedby referring to the LLR table.

The configuration of the ECC circuit 260 is described with referenceback to FIG. 2. The memory 262 is, for example, a volatile ornonvolatile semiconductor memory, and retains the LLR table describedabove. In the present embodiment, a plurality of LLR tables (three LLRtables in FIG. 2), LLR tables TW1, TW2, and TW3, are retained. These LLRtables TW are created in advance considering a threshold change due tothe writing and the erasing.

As described above, the threshold distribution changes due to variousinfluences. Therefore, for example, the LLR table that is suitable forthe threshold distribution illustrated in FIG. 4 may not be suitablewhen the threshold distribution in FIG. 4 changes.

Furthermore, there are various ways in which the threshold distributionchanges, depending on a cause of the change. For example, a writeoperation that is performed on cells may widen threshold distributionsof other memory cells to the high voltage side. This state isillustrated in FIG. 5. As illustrated, a shape of the thresholddistribution changes in such a manner that the upper edge thereofwidens. In the present example, a plurality of LLR tables TW is preparedconsidering an influence due to writing and erasing operations. Morespecifically, the LLR tables TW1, TW2, and TW3, for example, areoptimized according to the number of times a write operation and anerasing operation are performed on the block BLK.

The configuration of the ECC circuit 260 is described with referenceback to FIG. 2. The selector 263, for example, includes a volatile ornonvolatile semiconductor memory therein, and retains an order set tablein the internal semiconductor memory. Additionally, based on this orderset table, one of the LLR tables TW1, TW2, and TW3 in the memory 262 isselected, and the LLR table to be used for the data decoding is notifiedto the decoder 261. FIG. 6 illustrates a structure of the order settable.

As illustrated, in the order set table according to the presentembodiment, the order in which the LLR tables TW1, TW2, and TW3 are usedis defined for each of the six types of conditions (conditions A to F).That is, in the condition A, the LLR table TW1 is used first, TW2 next,and, TW3 last. In the condition B, the LLR table TW1 is use first, TW3next, and, TW2 last.

Each of the conditions A to F is, for example, the number of times(which is expressed as the number of times W/E) at least one of thewrite operation and the erasing operation is performed on areading-target block BLK. Specifically, for example, the conditions A toF are as follows.

Condition A: the number of times W/E=0 to 200

Condition B: the number of times W/E=201 to 400

Condition C: the number of times W/E=401 to 600

Condition D: the number of times W/E=601 to 800

Condition E: the number of times W/E=801 to 1000

Condition F: the number of times W/E=1001 or more

Furthermore, various methods can be employed to count the number oftimes W/E. The block is basically a unit for erasing, and data in thesame block are collectively erased. In this case, the number of timesthe erasing operation is performed on the block, as is, can be countedas the number of times of the erasing. However, for example, in the caseof a three-dimensionally-stacked NAND flash memory including memorycells stacked three-dimensionally on top of one another, it is alsopossible that the erasing is performed in units each less than a blocksize. In such a case, in a certain block, the numbers of times theerasing is performed in the units each less than the block size may becounted, and the counted numbers of times may be counted as the numberof times the block is erased. This erasure method is disclosed, forexample, in U.S. patent application Ser. No. 13/235,389 titled “NONVOLATILE SEMICONDUCTOR MEMORY DEVICE”, which is filed on Sep. 18, 2011.Furthermore, the erasure method is disclosed in U.S. patent applicationSer. No. 12/694,690 titled “NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE”,which filed on Jan. 27, 2010. Moreover, the erasure method is disclosedin U.S. patent application Ser. No. 13/483,610 titled “NONVOLATILESEMICONDUCTOR MEMORY DEVICE AND DATA ERASE METHOD THEREOF”, which isfiled on May 30, 2012. These Patent Applications are incorporated intheir entireties herein by reference.

Furthermore, as to a method of counting the write operation, forexample, when data are written to an arbitrary page of a certain block,this may be counted as one time. When data are further written toanother page of the certain block, this may be counted as two times. Thenumbers of times the writing is performed on the same block may beaccumulated (a method of performing the counting in page units).Alternatively, there is also a method (a method of performing thecounting in block units). According to the method, when data are writtento an arbitrary page of the block, this is counted as one time. However,even if writing is performed on another page without the erasing of theblock (or the erasing of a region smaller than a block, which includesthe arbitrary page) being performed thereafter, the writing is notcounted as one time. In the latter case, the number of times of theerasing and the number of times of the writing can be the same.

1.2 Operation

Next, a data read operation in the memory system 1 of the configurationdescribed above is described with a focus particularly on asoft-decision operation in the ECC circuit 260. FIG. 7 is a flowchart ofthe soft-decision operation.

As illustrated, first, the soft bit reading is performed (Step S10).That is, the processor 230 of the controller 200 transmits a blockaddress and a page address of a reading-target region to the NAND flashmemory 100, along with a soft bit reading command. When this operationis completed, in the NAND flash memory 100, the row decoder 120 selectsone of the pages, and, for example, as described in the example in FIG.4, a plurality of voltages V1 to V7 are applied as read voltages. Then,the sense amplifier 140 senses data (soft bits) that are read usingthese voltages V1 to V7, and then the read data are transmitted to thecontroller 200.

Next, the selector 263 of the ECC circuit 260 acquires the number oftimes W/E corresponding to the reading-target block BLK (Step S11). Thenumber of times W/E corresponding to each block BLK, for example, isretained, as a table, in the memory 220. Based on a physical address ofthe reading-target block BLK, the processor 230 reads the number oftimes W/E from the memory 220, and transfers the number of times W/E,which is read, to the selector 263.

When this operation is completed, based on the order set tableillustrated in FIG. 6, the selector 263 selects a table applicationorder (Step S12). That is, which of the conditions A to F in FIG. 6corresponds to the number of times W/E acquired in Step S11 isdetermined, and the corresponding table application order is selected.

Then, based on the table application order that is selected in Step S12,the selector 263 selects the highest-priority LLR table from thenot-selected LLR tables (Step S13). For example, in a case where thetable application order that corresponds to the condition A in FIG. 6 isselected, the highest-priority LLR table is the table TW1, the nexthighest-priority LLR table is the table TW2, and the lowest-priority LLRtable is the table TW3. It is here assumed that the table TW1 isselected. Then, the selector 263 reads the table TW1 from the memory262, and sets the read table TW1 for the decoder 261 (Step S14).

When this step is completed, the decoder 261 decodes (performs soft bitdecoding on) the read data, which are received from the NAND flashmemory 100, using the LLR table TW1 (Step S15). If the decoding succeeds(NO in Step S16), the read operation is successful, and the processingends.

In a case where the decoding fails (YES in Step S16), if there is anon-selected LLR table (YES in Step S17), the process returns to StepS13, and the soft bit decoding is performed using the next-priority LLRtable TW2 (Steps S13 to S15). In a case where there is no non-selectedLLR table (NO in Step S17), that is, when the decoding using any one ofthe three LLR tables TW1, TW2, and TW3 failed, the reading is regardedas a failure, and processing ends.

1.3 Effect According to the First Embodiment

According to the first embodiment, in the soft-decision processing forthe read operation, an optimal LLR table can be selected according tothe number of times W/E corresponding to the reading-target block BLK.For this reason, the time for error correction can be shortened and adata transfer speed in the memory system 1 can be improved.

As a NAND flash memory becomes more precise, higher correction abilityis required for an ECC circuit mounted in a controller of the NAND flashmemory. In order to realize the higher correction ability, an ECCcircuit that performs flexible determination such as the LDPC is morelikely to be mounted in the controller.

Before performing the soft decision, hard-decision processing isperformed. FIG. 8 is a conceptual diagram illustrating a flow of thehard-decision and soft-decision processing. During the hard-decisionprocessing, hard bit reading is performed first. The hard bit reading isdifferent from the soft bit reading, and data are read using one readvoltage that is set in advance (a read voltage assumed to be optimal).Then, the hard bit decoding processing is performed on the read data.

In a case where an error cannot be corrected by the hard bit decoding,then the soft-decision processing is performed. The soft bit reading isperformed first, and the soft bit reading is performed next. On thisoccasion, according to the present embodiment, a plurality of LLR tablesTW in consideration of the number of times W/E are prepared, andinformation of the LLR table TW that is suitable for the errorcorrection according to the number of times W/E is prepared as the orderset table. Generally, as a physical property of the NAND flash memory,the number of times W/E influences on the threshold distribution. Forthat reason, based on the order set table and the number of times W/E,the ECC circuit according to the present embodiment makes a selection insequential order among the prepared LLR tables TW, and performs the softbit decoding. That is, the plurality of LLR tables TW are prepared, butit is highly likely that the decoding using the LLR table that is usedfirst succeeds.

Furthermore, generally, a time period required to perform the soft bitdecoding one time is longer than a time period required to perform thehard bit decoding. Therefore, when the plurality of LLR tables is usedin the soft decision, the time period required to perform the readoperation may be considerably lengthened. For example, in the case ofdata that are difficult to correct, an influence of the above concern isremarkable. However, according to the present embodiment, the LLR tablesuitable for the block in which data are retained is used in sequentialorder. Therefore, the number of times of the soft bit decoding can beeffectively reduced, and the reading speed can be improved. This canlead to a remarkable effect on a host device for which maximum latencyto return the read data from the NAND flash memory is regulated.

According to the present embodiment as described above, high-speedreading is possible by preparing the plurality of LLR tables inconsideration of the number of times W/E and by dynamically changingpriority levels of the LLR tables according to the number of times W/Efor the reading-target block.

2. Second Embodiment

Next, a memory system according to a second embodiment is described.According to the second embodiment, instead of the number of times W/Eused in the first embodiment described above, the LLR tables areprepared according to the number of times of reading and one of them isselected. Only differences with the first embodiment will be describedbelow.

2.1 ECC Circuit 260

FIG. 9 is a block diagram of the ECC circuit 260 according to thepresent embodiment, in particular, elements related to the datadecoding.

A difference of a configuration according to the present embodiment fromthe configuration according to the first embodiment illustrated in FIG.2, is that the memory 262 has a plurality of LLR tables TR1, TR2, andTR3 (three LLR tables in an example in FIG. 9) that are created inconsideration of the threshold change due to the read operation insteadof the writing and the erasing. That is, the LLR tables TR1, TR2, andTR3 are optimized, for example, according to the number of times theread operation is performed on the block BLK.

Furthermore, as illustrated in FIG. 10, orders in which the LLR tablesTR1, TR2, and TR3 are used are defined for each of the six types ofconditions (conditions G to L) in the selector 263. That is, in thecondition G, the LLR table TR1 is used first, the TR2 next, and the TR3last. Then, each of the conditions G to L is the number of times theread operation is performed on the reading-target block BLK.Specifically, for example, the conditions G to L are as follows.

Condition G: the number of times of reading=0 to 300

Condition H: the number of times of reading=301 to 600

Condition I: the number of times of reading=601 to 900

Condition J: the number of times of reading=901 to 1200

Condition K: the number of times of reading=1201 to 1500

Condition L: the number of times of reading=1501 or more

2.2 Operation

Next, the data read operation in the memory system 1 of theconfiguration described above is described with a focus particularly onthe soft-decision operation in the ECC circuit 260. FIG. 11 is aflowchart for the soft-decision operation.

As illustrated, a difference of the present embodiment from the firstembodiment illustrated in FIG. 7 is described below.

That is, after Step S10, the selector 263 acquires the number of timesthe reading is performed on the reading-target block BLK (Step S20).That is, the number of times the reading is performed on every blockBLK, for example, is retained as a table in the memory 220. Based on thephysical address of the reading-target block BLK, the processor 230reads the number of times of reading from the memory 220, and transfersthe read number of times of reading to the selector 263.

Subsequently to Step S20, based on the order set table illustrated inFIG. 10, the selector 263 selects one of the LLR tables in accordancewith the table application order (Step S21). That is, based on one ofthe conditions G to L corresponding to the number of times of readingthat is acquired in Step S20, the corresponding table application orderis applied.

The others are the same as in the first embodiment. Moreover, the LLRtable that is used in Steps S13 to S15 is one of the LLR tables TR1,TR2, and TR3 that are prepared in consideration of the number of theread operation.

2.3 Effect According to the Present Embodiment

In the NAND flash memory, the read operation also has an influence onthe threshold distribution in the same manner as the write operation andthe erasing operation. Then, in some cases, a way of exerting theinfluence and the degree of the influence are different from those inthe write operation and the erasing operation.

Accordingly, according to the present embodiment, a plurality of LLRtables TR are prepared based on the number of times of reading, andinformation indicating the LLR table TR that is suitable for the errorcorrection according to the number of times of reading is prepared asthe order set table. The high-speed reading is possible by dynamicallychanging the priority levels of the LLR tables to be used according tothe number of times the reading is performed on the reading-targetblock.

3. Third Embodiment

Next, a memory system according to a third embodiment is described. Thethird embodiment is a combination of the first embodiment and the secondembodiment. According to the third embodiment, the LLR tables areprepared according to both of the number of times W/E and the number oftimes of reading and one of them is selected. Only differences with thefirst and second embodiments will be described below with two methods ofspecifying the present embodiment being taken as examples. Moreover, asdescribed above, the number of times W/E may be the number of times atleast one of the write operation and the erasing operation, and may bethe number of times corresponding to a sum of the number of times of thewrite operation and the number of times of the erasing operation. Thisis the same in embodiments subsequent to the third embodiment.

3.1 First Example

First, a first example is described. In the first example, two types ofLLR tables, that is, a LLR table TW that is created in consideration ofthe writing and the erasing and a LLR table TR that is created inconsideration of the reading, are used.

3.1.1 ECC Circuit 260

FIG. 12 is a block diagram of the ECC circuit 260 according to thepresent example, in particular, elements related to the data decoding.

A difference of a configuration according to the present example fromthe configurations according to the first and second embodimentsillustrated in FIGS. 2 and 9, respectively, is that the memory 262 has aplurality of LLR tables TW1 and TW2 (two LLR tables in FIG. 12) that arecreated in consideration of the threshold change due to the writing anderasing operations, and a plurality of LLR tables TR1 and TR2 (twotables in FIG. 12) that are created in consideration of the change inthreshold due to the read operation. That is, the LLR tables TW1 and TW2are optimized according to the number of times W/E, and the LLR tablesTR1 and TR2 are optimized according to the number of times of readoperations.

Furthermore, as illustrated in FIG. 13, orders in which the LLR tablesTW1, TW2, TR1, and TR2 are used are defined for each of the combinationsof the numbers of times W/E and the numbers of times of reading in theorder set table stored in the selector 263. That is, as illustrated inFIG. 13, in a case where both of the number of times W/E and the numberof times of reading are small, the LLR table TW1 is used first, TR1next, TW2 next, and TR2 last. Furthermore, in a case where the number oftimes W/E is small and the number of times of reading is large, the LLRtable TR1 is used first, TR2 next, TW1 next, and TW2 last. In a casewhere the number of times W/E is large and the number of times ofreading is small, the LLR table TW1 is used first, TW2 next, TR1 next,and TR2 last. In a case where both of the number of times W/E and thenumber of times of reading are large, the LLR table TW2 is used first,TR2 next, TW1 next, and TR1 last.

Moreover, whether the number of times W/E is large or small, or whetherthe number of times of reading is large or small can be determined, forexample, based on the following reference. Of course, the followingreference is only one example.

The number of times W/E is smaller than 500: the number of timesW/E=small

The number of times W/E is equal to or larger than 500: the number oftimes W/E=large

The number of times of reading is smaller than 1000: the number of timesof reading=small

The number of times of reading is equal to larger than 1000: the numberof times of reading=large

3.1.2 Operation

Next, the data read operation in the memory system 1 of theconfiguration described above is described with a focus particularly onthe soft-decision operation in the ECC circuit 260. FIG. 14 is aflowchart of the soft-decision operation.

As illustrated, a difference of the present example from the first andsecond embodiments illustrated in FIGS. 7 and 11, respectively, isdescribed below.

That is, after Step S10, the selector 263 acquires the number of timesW/E for the reading-target block BLK and the number of times of reading(Step S30). That is, the number of times W/E and the number of times ofreading are retained for each block BLK as tables in the memory 220.That is, based on the physical address of the reading-target block BLK,the processor 230 reads both of the number of times W/E and the numberof times of reading from the memory 220, and transfers the number oftimes of W/E and the number of times of reading, which are read, to theselector 263.

Subsequently to Step S30, based on the order set table illustrated FIG.13, the selector 263 selects one of the LLR tables in accordance withthe table application order (Step S31). That is, based on one of theconditions in FIG. 13 corresponding to the number of times W/E and thenumber of times of reading, which are acquired in Step S30, thecorresponding table application order is applied.

The others are the same as in the first embodiment. Here, the LLR tableused in Steps S13 to S15 is one of the LLR tables TW1 and TW2 that arecreated in consideration of the writing and erasing operations or one ofthe LLR tables TR1 and TR2 that are created in consideration of the readoperation.

3.2 Second Example

Next, a second example is described. In the second example, a pluralityof LLR tables TWR created in consideration of three operations, that is,the writing, the erasing, and the reading is used.

3.2.1 ECC Circuit 260

FIG. 15 is a block diagram of the ECC circuit 260 according to thepresent example, in particular, elements related to the data decoding.

A difference of the configuration according to the present example fromthe configuration according to the first example illustrated in FIG. 12,is that the memory 262 has a plurality of LLR tables TWR1, TWR2, TWR3,and TWR4 (four LLR tables in an example in FIG. 15) that are created, inconsideration of the threshold change due to three operations, that is,the writing, erasing, and read operations. That is, each of these fourLLR tables TWR1, TWR2, TWR3, and TWR4 is optimized according to both ofthe number of times W/E and the number of times of reading.

Furthermore, as illustrated in FIG. 16, orders in which the LLR tablesTWR1, TWR2, TWR3, and TWR4 are used are defined for each combination ofthe numbers of times W/E and the numbers of times of reading in theorder set table stored in the selector 263. That is, in FIG. 16, in acase where both of the number of times W/E and the number of times ofreading are small, the LLR tables are used in this order: TWR1, TWR2,TWR3, TWR4. In a case where the number of times W/E is small and thenumber of times of reading is large, the LLR tables are used in thisorder: TWR2, TWR1, TWR4, and TWR3. A criteria to determine whether thenumber of times W/E and the number of times of reading are large orsmall, for example, is the same as the first example.

3.2.2. Operation

A soft-decision operation relating to the present example is same as theone described in the first example with reference to FIG. 14.

3.3 Effect According to the Third Embodiment

According to the third embodiment, an optimal LLR table can be selectedbased on both of the number of times W/E and the number of times ofreading that are carried out in the NAND flash memory. Therefore,preciseness of correction can be improved further than in the first andsecond embodiments. Moreover, in FIGS. 13 and 16, two types of cases areillustrated as conditions, that is, the case where the number of timesW/E and the number of times of reading are small and the case where thenumber of times W/E and the number of times of reading are large, aredescribed as examples. However, three or more cases may be set as theconditions, such as a case where the number of times W/E and the numberof times of reading are approximately at an intermediate level betweensmall and large.

4. Fourth Embodiment

Next, a memory system according to a fourth embodiment is described.According to the fourth embodiment, the LLR table is selected accordingto the physical address, that is, a position of the reading-targetregion, instead of the number of times W/E according to the firstembodiment described above. Only a difference with the first embodimentwill be described below.

4.1 ECC Circuit 260

FIG. 17 is a block diagram of the ECC circuit 260 according to thepresent embodiment, in particular, elements related to the datadecoding.

A difference of a configuration according to the present embodiment fromthe configuration according to the first embodiment illustrated in FIG.2 is that a plurality of LLR tables T1, T2, and T3 (three LLR tables inan example in FIG. 17) that is stored in the memory 262 are not limitedto the ones that are prepared in consideration of the number of times WEand the number of times of reading. For example, the LLR table T1 maycorrespond to an average threshold distribution within a memory cellarray, and the other LLR tables T2 and T3 may be different from the LLRtable T1 and be different from each other.

Furthermore, an order in which one of the three LLR tables T1, T2, andT3 are used is defined in the order set table stored in the selector263, for each of physical addresses of a region that is accessed forreading, as illustrated in FIG. 18. That is, in a case where thephysical address designates a first region, the LLR table applies inthis order: T1, T2, T3. In a case where a second region different fromthe first region is designated, the LLR table applies in this order: T2,T1, T3. In a case where a third region different from the first andsecond regions is designated, the LLR table applies in this order: T3,T2, T1.

4.2 Operation

Next, the data read operation in the memory system 1 of theconfiguration described above is described with a focus particularly onthe soft-decision operation in the ECC circuit 260. FIG. 19 is aflowchart of the soft-decision operation.

As illustrated, a difference of the present embodiment from the firstembodiment illustrated in FIG. 7 is described below.

That is, after Step S10, the selector 263 acquires the physical addressof the reading-target region (Step S40). The host apparatus 300 issues areading command to the controller 200 using a logical address. Thecontroller 200 maintains a table showing a relationship between (i) thislogical address and (ii) a physical address of a block BLK and a page inthe memory cell array 110 of the NAND flash memory 100, for example, inthe memory 220. Then, for example, the processor 230 converts thelogical address into the physical address using this table, and issuesthe reading command to the NAND flash memory 100. The processor 230transmits the physical address that is obtained in this manner, also tothe selector 263 of the ECC circuit 260.

Subsequently to Step S40, based on the order set table illustrated inFIG. 18, the selector 263 selects one of the LLR tables in accordancewith the table application order (Step S41). That is, the correspondingtable application order is selected according a region that isdesignated by the received physical address.

The others are the same as in the first embodiment. Moreover, the LLRtable that is used in Steps S13 to S15 is one of the LLR tables T1, T2,and T3.

4.3 Specific Example

Next, specific examples of the first and third regions that aredescribed with reference to FIG. 18 is briefly described.

4.3.1 First Example

A first example corresponds to a case where a region is designated on aper-block basis. FIG. 20 illustrates one example of a plane layout of ablock BLK in the memory cell array 110. In the present example, thememory cell array 110 includes two planes PN0 and PN1, and each of theplanes includes 16 blocks BLK00 to BLK33.

In the present example, the blocks BLK that have the most excellentproperty are surrounded by other blocks, and are blocks (a block BLK11,BLK12, BLK21, or BLK22 in the planes PN0 and PN1) that are notpositioned at the border of the plane. These blocks are equivalent tothe first region.

The blocks BLK that have the next most excellent property are surroundedby other blocks, but are blocks (a block BLK31 or BLK32 in the planePN0, or a block BLK01 or BLK02 in the plane PN1) that are positioned atthe border of the plane. These blocks are equivalent to the secondregion.

Blocks (blocks BLK00, BLK01, BLK02, BLK03, BLK10, BLK13, BLK20, BLK23,BLK30, and BLK33 in the plane PN0, and blocks BLK00, BLK03, BLK10,BLK13, BLK20, BLK23, BLK30, BLK31, BLK32, and BLK33 in the plane PN0)that are positioned at the end portion of the memory cell array 110 havedisrupted regularity in a block layout, and thus have comparatively-poorproperty. These blocks are equivalent to the third region.

As described above, the order in which one of the LLR tables is selectedmay be changed according to a position of the block BLK.

4.3.2 Second Example

A second example corresponds to a case where a region is designated on aper-word line basis. FIG. 21 is a cross-sectional diagram of a NAND cellthat is included in each block BLK, and is an equivalent-circuit diagramthereof. As one example, FIG. 21 illustrates a configuration in which aNAND string has eight memory cell transistors MT0 to MT7, and in whichselect transistors ST0 to ST1 and a memory cell transistor MT arestacked above a semiconductor substrate.

As described, four-layered inter-connection layer 11 that functions as aselect gate line SGS, an eight-layered inter-connection layer 12 thatfunctions as word lines WL0 to WL7, and four-layered inter-connectionlayer 13 that functions as a select gate line SGD are sequentiallystacked on a p-type well region 10. An insulating film, which is notillustrated, is formed between each of the inter-connection layers thatare stacked on top of one another.

Then, a pillar-shaped conductor 14 is formed so as to pass through theseinter-connection layers 13, 12, and 11 and reach the well region 10. Agate insulating film 15, a charge storage layer (an insulating film or aconductive film) 16, and a block insulating film 17 are formed on aflank surface of the conductor 14, and the memory cell transistor MT andthe select transistors ST1 and ST2 are formed as a result. The conductor14 functions as an electric current path for the NAND string and is aregion in which a channel of each transistor is formed. Then, the upperend of the conductor 14 is connected to a metal inter-connection layer18 that functions as a bit line BL which extends to the NAND string andthe sense amplifier 140. Moreover, a n+ type impurity diffusion layer 19is formed within a surface region of the well region 10, and thediffusion layer 19 is connected to a source line SL, which is notillustrated.

A plurality of configurations, each of which is described above, isarranged in horizontal directions and a depth direction of paper onwhich FIG. 21 is drawn, and the block BLK is formed by a set of aplurality of the NAND strings. The block BLK, for example, is a unit forerasing, but data may be erased in units smaller than the block BLK.

The configuration of the memory cell array 110 may be otherconfigurations. The other configuration of the memory cell array 110 isdisclosed, for example, in U.S. patent application Ser. No. 12/407,403filed on Mar. 19, 2009, which is titled “THREE-DIMENSIONAL STACKEDNON-VOLATILE SEMICONDUCTOR MEMORY”. Furthermore, a configuration of thememory cell array 110 is disclosed in U.S. patent application Ser. No.12/406,524, filed on Mar. 18, 2009, which is titled THREE DIMENSIONALSTACKED NONVOLATILE SEMICONDUCTOR MEMORY, U.S. patent application Ser.No. 12/679,991, filed on Mar. 25, 2010, which is titled “NON-VOLATILESEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME”, andU.S. patent application Ser. No. 12/532,030, filed on Mar. 23, 2009,which is titled “SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING THESAME”. These Patent Applications are incorporated in their entiretiesherein by reference.

In the present example, a memory cell that corresponds to a word line WLthat is not adjacent to the select gate lines SGD and SGS, that is, aword line WL that is vertically disposed between other word lines WL,has excellent property. For that reason, for example, word lines WL1 toWL6 are equivalent to the first region, a word line WL7 that is adjacentto the select gate line SGD is equivalent to the second region, and aword line WL0 that is adjacent to the select gate line SGS is equivalentto the third region. Of course, each of the second and third regions mayinclude a plurality of word lines WL.

In this manner, the order in which one of the LLR tables is used may bechanged according to a position of the word line WL to be accessed.

4.4 Effect According to the Present Embodiment

Property of a memory cell may vary according to a physical position inthe NAND flash memory. According to the present embodiment, thehigh-speed reading is possible by dynamically switching to the suitableLLR table according to the physical position of the reading-targetregion.

Moreover, the LLR tables in the present example may be created inconsideration of a position within the memory cell array. Then, one theLLR tables may be selected in such a manner that a region which isactually accessed and the position considered when the LLR table iscreated are consistent with each other.

5. Fifth Embodiment

Next, a memory system according to a fifth embodiment is described.Unlike in the first to fourth embodiments, in the fifth embodiment, anoptimal LLR table is selected based on past correction historyinformation for each LLR table, not based on the order set table that isprepared in advance. Only a difference with the first and fourthembodiments will be described below.

5.1 ECC Circuit 260

FIG. 22 is a block diagram of the ECC circuit 260 according to thepresent embodiment, in particular, elements related to the datadecoding.

As illustrated, the memory 262 according to the present embodimentincludes a plurality of LLR tables T1, T2, T3, . . . Tn (n tables inFIG. 17, and n is a natural number that is equal to or larger than 2).These LLR tables T1 to Tn are not limited to ones that are prepared inconsideration of the number of times W/E and the number of times ofreading, in the same manner as in the fourth embodiment.

As described above, in the same manner as in the first embodiment, thedecoder 261 performs the hard-decision decoding processing and thesoft-decision decoding processing on data read from the NAND flashmemory 100, and transmits the decoded data to the host apparatus 300. Onthis occasion, during the soft-decision decoding processing, data aredecoded using any one of the LLR tables T1 to Tn within the memory 262.Then, the information that the decoding succeeds or fails is transmittedto the selector 263.

The selector 263 includes, for example, a volatile or nonvolatilesemiconductor memory therein, and maintains a history table in thesemiconductor memory. Then, based on this history table, one of the LLRtables T1 to Tn in the memory 262 is selected, and the LLR table to beused for the data decoding is notified to the decoder 261. FIG. 23illustrates a structure of the history table.

The history table indicates information relating to the number of timesthe decoding succeeds in the past using each of the LLR tables T1 to Tn.In FIG. 23, the number of times correction succeeds (the number of timesof successful correction) is retained for each of the LLR tables T1 toTn. As illustrated, in a case where the LLR table T1 is used, thedecoding succeeds only N1 times in the past, and in a case where the LLRtable T2 is used, the decoding succeeds only N2 times in the past (N1 toNn are natural numbers). The selector 263 updates the history tablebased on information that the decoding succeeds, which is received fromthe decoder 261.

5.2 Operation

Next, the data read operation in the memory system 1 of theconfiguration described above is described with a focus particularly onthe soft-decision operation in the ECC circuit 260. FIG. 24 is aflowchart of the soft-decision operation.

As illustrated, first, the soft bit reading is performed (Step S10).Step S10 is the same as the first embodiment. Next, the selector 263 ofthe ECC circuit 260 refers to the history table, and selects an LLRtable that has the largest number of times of successful correction,from non-selected LLR tables (Step S50). That is, the selector 263selects an LLR table that has the largest number of times the datadecoding succeeds in the past, in other words, an LLR table that has thegreatest likelihood that the decoding will succeed. Then, the selector263 reads the selected LLR table from the memory 262, and sets theselected LLR table for the decoder 261 (Step S14).

When this step is completed, the decoder 261 decodes (performs the softbit decoding on) read data received from the NAND flash memory 100,using the LLR table that is set (Step S15). If the decoding succeeds (NOin Step S16), the decoder 261 notifies the selector 263 of theinformation that the decoding succeeds, and the selector 263 updates thenumber of times of successful correction in the history table (StepS51). That is, for example, in a case where the LLR table T1 is selectedand the data decoding succeeds, the selector 263 adds “+1” to the numberN1 corresponding to the LLR table T1 in the history table.

In the case where the decoding fails (YES in Step S16), if there is anon-selected LLR table (YES in Step S17), the process returns to StepS50 and the soft bit decoding is performed using the LLR table that hasthe next largest number of times of successful correction (Steps S14 toS15). In the case where there is no non-selected LLR table (NO in StepS17), that is, in a case where the decoding did not succeed with any oneof the n LLR tables T1 to Tn, the reading is regarded as a failure andthe process ends.

5.3 Effect According to the Fifth Embodiment

According to the fifth embodiment, past performance of each LLR table isrecorded as the history table, and, based on the recorded pastperformance, a selection is made in sequential order among the LLRtables that are thought to have the high likelihood of being able to becorrected. Therefore, in the same manner as in the first embodiment,data can be efficiently corrected.

Moreover, in the fifth embodiment, the number of times the correctionsucceeds is recorded in the history table, but the number of times thecorrection fails may be recorded instead. In this case, in Step S50 inFIG. 24, the LLR table corresponding to the smallest number of times thecorrection fails may be selected.

Furthermore, the history table may be created with a default value inadvance at the time of factory shipment of the memory system 1, in whichcase the history table that is set by default is updated whenever thedata reading succeeds.

In a case where the default history table is not prepared, the order inwhich one of the LLR tables is selected may be retained. That is, whenthe NAND flash memory 100 is used for the first time, the history tablehas not been created, or the history table itself is not present.Furthermore, soon after the NAND flash memory 100 starts to be used,there is a likelihood that an amount of information recorded in thehistory table is small and does not have sufficient reliability. In sucha case, the LLR table may be selected according to the order that isprescribed in advance, and, when the number of times of reading exceedsa fixed number, the history table may start to be used. Alternatively,the LLR table may be selected according to the methods that aredescribed in the first and fourth embodiments, until the number of timesof reading exceeds a fixed number.

Moreover, the processor 230 may write the history table to a specificregion (a ROM fuse region or the like) of the NAND flash memory 100,along with the LLR table or information, such as the number of times W/Eor the number of times of reading, in such a manner that the historytable is not lost when the memory system 1 is powered off. Thereafter,when the memory system 1 is powered on, the history table read from theNAND flash memory 100 may be set for the selector 263.

6. Sixth Embodiment

Next, a memory system according to a sixth embodiment is described. Inthe sixth embodiment, the history table used in the fifth embodiment isused for each physical address, and thus the sixth embodiment isequivalent to a combination of the fourth embodiment and the fifthembodiment. Only a difference from the fifth embodiment will bedescribed below.

6.1 History Table

As described above, in the configuration in FIG. 22, which is describedin the fifth embodiment, the selector 263 according to the presentembodiment includes a plurality of history tables. The plurality ofhistory tables is referred to as a history table group.

FIG. 25 illustrates a structure of the history table group. Asillustrated, the history table group includes the plurality of historytables that are correlated with blocks BLK0 to BLKm (m is a naturalnumber, and (m+1) is the number of blocks within the memory cell array110), respectively.

That is, the history table that is correlated with block BLK0 retainsthe number of times the data decoding succeeds while reading data fromthe block BLK0, for each LLR table, the history table that is associatedwith the block BLK1 retains the number of times the data decodingsucceeds while reading data from the block BLK1, for each LLR table, andso forth.

Of course, as described in the fourth embodiment, the history tableprepared for each block BLK is only an example, and a plurality ofhistory tables may be provided according to the physical address. Forexample, as described in the second example of the fourth embodiment, aplurality of word lines WL may be categorized into a plurality of zones(for example, eight word lines are divided into three zones, and soforth), and the history table may be prepared for each zone.

6.2 Operation

Next, the data read operation in the memory system 1 of theconfiguration described above is described with a focus particularly onthe soft-decision operation in the ECC circuit 260. FIG. 26 is aflowchart of the soft-decision operation.

As illustrated, a difference of the present embodiment from the fifthembodiment illustrated in FIG. 24 is described below.

That is, after Step S10, the selector 263 acquires the physical addressof the reading-target region (Step S40). This step is the same as theone described in the fourth embodiment.

Subsequently to Step S40, the selector 263 selects the correspondinghistory table from the history table group illustrated in FIG. 25,according to the physical address that is received in Step S40 (StepS60). Thereafter, based on the history table that is selected in StepS60, the processing operations in Step S50 and later are performed in amanner similar to the ones described in the fifth embodiment.

6.3 Effect According to the Sixth Embodiment

As described in the fourth embodiment, the property of the memory cellcan differ depending on a physical position thereof. For that reason, anoptimal LLR table may differ depending on the physical position.According to the present embodiment, the LLR table suitable for eachregion can be selected by preparing the history table for each region(for example, every block BLK) within the memory cell array.

Moreover, in a case where the LLR table is prepared on a per-blockbasis, there is no need to establish a one-to-one correspondence betweenthe block and the LLR table. For example, the LLR may be prepared foreach of the plurality of blocks, and may be prepared for only a blockthat is expected to have a low property when compared with others.

Alternatively, the tables may be prepared only for blocks that have beenaccessed most recently. Specifically, the LLR tables may be preparedonly for blocks that were set to be a reading target within the mostrecent reading access of 50 times. Then, the LLR tables for blocks thatwere not set to be the reading target within the most recent readingaccess of 50 times may be discarded.

Also, the history table according to the present embodiment may also bewritten to the NAND flash memory 100 when the memory system is poweredoff.

7. Seventh Embodiment

Next, a memory system according to a seventh embodiment is described. Inthe seventh embodiment, the history table used in the fifth embodimentis prepared for each range of number of times W/E, and therefore theseventh embodiment is equivalent to a combination of the firstembodiment and the fifth embodiment. Only a difference with the fifthembodiment will be described below.

7.1 History Table

The selector 263 according to the present embodiment retains the historytable group in the same manner as the selector 263 according to thesixth embodiment. FIG. 27 illustrates a structure of a history tablegroup according to the present embodiment. As illustrated, the historytable group includes a plurality of history tables (k history tables andk is a natural number that is equal to or larger than 2) that arecorrelated with a range of the numbers of times W/E, respectively, andcorresponds to the cases of first to k-th ranges within which the numberof times W/E falls. An example of each of the ranges is described below.

First range: the number of times W/E is equal to or larger than 0, butis smaller than 100

Second range: the number of times WE is equal to or larger than 100, butis smaller than 200

Third range: the number of times W/E is equal to or larger than 200, butis smaller than 300

k-th range: the number of times W/E is equal to or larger than 1000

That is, in a case where the number of times of access for reading to acertain block falls within the first range, an LLR table that has thelargest number of times of successful correction is selected from thehistory tables that correspond to the first range.

7.2 Operation

Next, the data read operation in the memory system 1 of theconfiguration described above is described with a focus particularly onthe soft-decision operation in the ECC circuit 260. FIG. 28 is aflowchart of the soft-decision operation.

As illustrated, a difference of the present embodiment from the fifthembodiment illustrated in FIG. 24 is described below.

That is, after Step S10, the selector 263 acquires the number of timesW/E for the reading-target region (Step S11). This processing is thesame as the one described in the first embodiment.

Subsequently to Step S11, the selector 263 selects the correspondinghistory table from the history table group illustrated in FIG. 27,according to the number of times W/E that is received in Step S11 (StepS70). Thereafter, based on the history table that is selected in StepS70, the processing operations in Step S50 and later are performed in asimilar manner as the ones described in the fifth embodiment.

7.3 Effect According to the Present Embodiment

As described in the first embodiment, the property of the memory cellcan differ depending on the number of times W/E. For that reason, anoptimal LLR table may differ depending on the number of times W/E.According to the present embodiment, a suitable LLR table can beselected by preparing the history table for each range of the number oftimes W/E.

Moreover, in the present embodiment, the history table is prepared inassociation with the number of times W/E. However, the history table maybe prepared in association with the number of times of reading as in thesecond embodiment, and the history table may be prepared in associationwith both the number of times W/E and the number of times of reading asin the third embodiment. In a case where the history table is associatedwith both the number of times W/E and the number of times of reading,the number of times of reading may increase by +1 each time theoperation is performed two times, whereas the number of times W/E isincreased by +1 each time the operation is performed one time. Thereason for this is because an influence on the memory cell is consideredto be larger in the writing and erasing operations than in the readoperation.

Also, the history table group according to the present embodiment mayalso be written to the NAND flash memory 100 when the memory system ispowered off.

8. Modification Example and the Like

As described above, in the memory system according to the presentembodiment, a plurality of LLR tables is prepared and the order in whichone of the LLR tables is selected for the soft-decision decoding isdynamically changed according to the number of times W/E, the number oftimes of reading, the physical address, and/or the number of times ofsuccessful correction. As a result, under various conditions forreading, a more suitable LLR table can be selected, and an errorcorrection speed can be improved.

Moreover, no limitation to the embodiments described above is imposedand various modifications to the embodiments are possible. For example,the threshold distribution moves to the low voltage side as passage oftime. That is, as opposed to the change in distribution, which isdescribed with reference to FIG. 5, the lower edge of the thresholddistribution widens to the low voltage side. The LLR tables may beprepared in consideration of this influence.

That is, the LLR tables in consideration of the writing and erasingoperations are prepared in the first embodiment, and the LLR tablesinconsideration of the read operation are prepared in the secondembodiment. Instead, a plurality of LLR tables that may be prepared inconsideration of the passage of time since data were written to thememory. In this case, for example, the controller 200 includes a timercircuit and records time when data were written for each block or everypage. Then, the LLR table may be selected according to the passage oftime from the time when the writing was performed. Of course, the LLRtable in consideration of the passage of time may be used in the firstto seventh embodiments described above, and a plurality of historytables may be prepared according to the passage of time. In a case wheresuch LLR tables are used in the fifth embodiment, for example, aplurality of history tables may be prepared for each range of passedtime periods, and an optimal history table may be selected according tothe passage of time in an access-target region.

Furthermore, in the fourth and seventh embodiments, the LLR table may beprepared for each access region in accordance with the number of timesof writing, erasing, and/or reading. That is, the LLR table or thehistory table may be prepared and selected according to at least one ofthe numbers of times of writing, erasing, and reading and the positionof the access region.

Additionally, in the fifth to seventh embodiments, for example, the ECCcircuit 260 may further include a counter and the counter may count thenumber of times the decoding succeeds. Then, this result of the countingis stored in the selector.

Moreover, the LLR tables used in the third embodiment are created inconsideration of the threshold change due to the write operation, theerasing operation, and the read operation. However these operations donot necessarily need to be considered, and it is sufficient thatdifferent LLR tables are prepared as described in the fifth embodiment.Then, a selection may be made according to the number of times W/E orthe number of times of reading. This is also the same for the first andsecond embodiments.

In the above embodiments, the NAND flash memory is described as anexample of the semiconductor memory device. However, the semiconductormemory device is not limited to the NAND flash memory, and theembodiments described above can apply to all storage devices in whichthe soft-decision processing is carried out.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A memory system comprising: a nonvolatilesemiconductor memory; a controller configured to maintain a plurality oflog likelihood ratio (LLR) tables for predicting a value of data readfrom the nonvolatile semiconductor memory, count a number of times thateach of write operations, erase operations, and read operations havebeen carried out with respect to each unit storage region of thenonvolatile semiconductor memory, determine an order in which the LLRtables are referred to, based on the counted number of the readoperations and one of the counted number of the write operations and thecounted number of the erase operations, which correspond to a targetunit storage region of a read operation, and carry out decoding of dataread from the target unit storage region of the read operation, usingone of the LLR tables selected according to the determined order.
 2. Thememory system according to claim 1, wherein the plurality of LLR tablesincludes a first plurality of LLR tables that is different depending onthe number of times of the write operations and the number of times ofthe erase operations, and a second plurality of LLR tables that isdifferent depending on the number of times of the read operations. 3.The memory system according to claim 1, wherein the unit storage regionis a unit of erasing data from the nonvolatile semiconductor memory. 4.The memory system according to claim 1, wherein the controller carriesout the decoding using a next LLR table in the determined order, whenthe decoding using the selected LLR table fails.
 5. The memory systemaccording to claim 1, wherein the data read from the target unit storageregion include a plurality of values that are sensed using differentread voltages.
 6. A memory system comprising: a nonvolatilesemiconductor memory; a controller configured to maintain a plurality oflog likelihood ratio (LLR) tables for predicting a value of data readfrom the nonvolatile semiconductor memory, determine an order in whichthe LLR tables are referred to, based on a physical location of a targetunit storage region of a read operation, and carryout decoding of dataread from the target unit storage region, using one of the LLR tablesselected according to the determined order.
 7. The memory systemaccording to claim 6, wherein the controller determines the order to bea first order when the target unit storage region is located at an endof the storage regions, and to be a second order different from thefirst order when the target unit storage region is not located at theend of the storage regions.
 8. The memory system according to claim 7,wherein the unit storage region is a unit of erasing data from thenonvolatile semiconductor memory.
 9. The memory system according toclaim 6, wherein the controller determines the order to be a first orderwhen the target unit storage region is connected to a first word line,and to be a second order different from the first order when the targetunit storage region is connected to a second word line that is locatedouter than the first word line in a thickness direction of thenonvolatile semiconductor memory.
 10. The memory system according toclaim 6, wherein the unit storage region is a unit of reading data fromthe nonvolatile semiconductor memory.
 11. The memory system according toclaim 6, wherein the controller carries out the decoding using a nextLLR table in the determined order, when the decoding using the selectedLLR table fails.
 12. The memory system according to claim 6, wherein thecontroller is further configured to count a number of times decoding ofdata that are read using each of the LLR tables was successful, withrespect to each of the unit storage regions, and determine the orderalso based on the counted numbers corresponding to the target unitstorage region.
 13. The memory system according to claim 6, wherein thecontroller selects one of the LLR tables that corresponds to the targetunit storage region and of which counted number is the smallest, first.14. The memory system according to claim 6, wherein the data read fromthe target unit storage region include a plurality of values that aresensed using different read voltages.
 15. A memory system comprising: anonvolatile semiconductor memory; a controller configured to maintain aplurality of log likelihood ratio (LLR) tables for predicting a value ofdata read from the nonvolatile semiconductor memory, count a number oftimes decoding of data that are read using each of the LLR tables wassuccessful, determine an order in which the LLR tables are referred to,based on the counted number, and carry out decoding of data read from atarget unit storage region of a read operation, using one of the LLRtables selected according to the determined order.
 16. The memory systemaccording to claim 15, wherein the controller selects one of the LLRtables of which counted number is the smallest, first.
 17. The memorysystem according to claim 15, wherein the controller is furtherconfigured to count a second number of times write and erase operationshave been carried out with respect to each unit storage region of thenonvolatile semiconductor memory, count the number of times decoding ofdata that are read using each of the LLR tables was successful withrespect to each range of the number of times of the write and eraseoperations, and determine the order also based on the second countednumber.
 18. The memory system according to claim 15, wherein thecontroller is further configured to count a second number of times readoperations have been carried out with respect to each unit storageregion of the nonvolatile semiconductor memory, count the number oftimes decoding of data that are read using each of the LLR tables wassuccessful with respect to each range of the number of times of thewrite and erase operations, and determine the order also based on thesecond counted number.
 19. The memory system according to claim 15,wherein the controller carries out the decoding using a next LLR tablein the determined order, when the decoding using the selected LLR tablefails.
 20. The memory system according to claim 15, wherein the dataread from the target unit storage region include a plurality of valuesthat are sensed using different read voltages.